Name
Abstract | ||
|---|---|---|
This paper presents a 12-bit 50-MSPS pipelined Analog-to-Digital converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid time-sharing architecture without Sample-and-Hold Amplifier (SHA) is employed to make a trade-off between the performance and power consumption of the ADC. An SHA-less front-end is adopted, including a matched sampling network to considerably reduce aperture error between a 2.5-bit Multiplying Digital-to-Analog Converter (MDAC) and a Sub-Analog-to-Digital converter (SUBADC). Some efforts to optimize operational amplifier (opamp) are also made. Simulation results show that the ADC achieves 83.2-dB SFDR and 73.4-dB SNDR for input signal up to Nyquist range. The ADC consumes 26.6mW at sampling rate of 50MHz from 1.2-V supply voltage. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASICON.2011.6157349 | ASICON |
Keywords | Field | DocType |
cmos process,cmos integrated circuits,analogue-digital conversion,multiplying digital-to-analog converter,voltage 1.2 v,operational amplifier,operational amplifiers,sha,size 16 nm,opamp,sample-and-hold amplifier,sub-analog-to-digital converter,subadc,msps pipelined analog-to-digital converter,frequency 50 mhz,mdac,sample and hold circuits,word length 12 bit,front end,switches,logic gates,logic gate,capacitance,time sharing | Computer science,Sampling (signal processing),Effective number of bits,Electronic engineering,Analog-to-digital converter,CMOS,Successive approximation ADC,Operational amplifier,Integrating ADC,Amplifier | Conference |
Volume | Issue | ISSN |
null | null | 2162-7541 E-ISBN : 978-1-61284-191-5 |
ISBN | Citations | PageRank |
978-1-61284-191-5 | 0 | 0.34 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen Shu | 1 | 0 | 0.34 |
| Guanghua Shu | 2 | 57 | 9.11 |
| Jun Xu | 3 | 0 | 1.69 |
| Fan Ye | 4 | 34 | 21.14 |
| Junyan Ren | 5 | 154 | 41.40 |