Name
Abstract | ||
|---|---|---|
Functionality and combinationality are two main issues that have to be dealt with in cyclic combinational circuits, which are combinational circuits containing loops. Cyclic circuits are combinational if nodes within the circuits have definite values under all input assignments. For a cyclified circuit, we have to check whether it is combinational or not. Thus, this paper proposes an efficient two-stage algorithm to verify the combinationality of cyclic circuits. A set of cyclified IWLS 2005 benchmarks are performed to demonstrate the efficiency of the proposed algorithm. Compared to the state-of-the-art algorithm, our approach has a speedup of about 4000 times on average. |
Year | Venue | Keywords |
|---|---|---|
2015 | DATE | logic design,combinational circuits,algorithm design and analysis,open systems,logic gates,benchmark testing,voting |
Field | DocType | ISSN |
Boolean circuit,Sequential logic,Computer science,Parallel computing,Combinational logic,Electronic circuit,Speedup,Approximate computing | Conference | 1530-1591 |
Citations | PageRank | References |
1 | 0.37 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wan-Chen Weng | 1 | 2 | 0.75 |
| Yung-Chih Chen | 2 | 413 | 39.89 |
| Jui-Hung Chen | 3 | 2 | 0.75 |
| Ching-Yi Huang | 4 | 58 | 10.06 |
| Wang Chun-Yao | 5 | 251 | 36.08 |