Paper Info
Title
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power
Abstract
Recently, an emerging non-volatile memory called Racetrack Memory (RM) becomes promising to satisfy the requirement of increasing on-chip memory capacity. RM can achieve ultra-high storage density by integrating many bits in a tape-like racetrack, and also provide comparable read/write speed with SRAM. However, the lack of circuit-level modeling has limited the design exploration of RM, especially in the system-level. To overcome this limitation, we develop an RM circuit-level model, with careful study of device configurations and circuit layouts. This model introduces Macro Unit (MU) as the building block of RM, and analyzes the interaction of its attributes. Moreover, we integrate the model into NVsim to enable the automatic exploration of its huge design space. Our case study of RM cache demonstrates significant variance under different optimization targets, in respect of area, performance, and energy. In addition, we show that the cross-layer optimization is critical for adoption of RM as on-chip memory.
Year
DOI
Venue
2015
10.1109/ASPDAC.2015.7058988
ASP-DAC
Keywords
Field
DocType
read-write speed,racetrack memory,integrated circuit modelling,circuit layout,cache storage,sram chips,nvsim,rm cache,ultra-high storage density,circuit optimisation,mu,device configurations,nonvolatile memory,quantitative modeling,tape-like racetrack,cross-layer optimization,integrated circuit design,sram,macrounit,circuit layouts,rm circuit-level model,on-chip memory capacity
Design space,Semiconductor memory,Computer science,Cache,Static random-access memory,Electronic engineering,Macro,Computer memory,Design exploration,Racetrack memory
Conference
ISSN
Citations 
PageRank 
2153-6961
21
0.92
References 
Authors
10
6
Name
Order
Citations
PageRank
Chao Zhang142338.17
Guangyu Sun21920111.55
Weiqi Zhang3482.97
Fan Mi4210.92
Hai Li52435208.37
Weisheng Zhao6730105.43