Paper Info
Title
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits
Abstract
Traditionally, we expect that circuit designs can be executed without errors. However, for error resilient applications such as image processing, 100% correctness is not necessary. By pursuing less than 100% correctness, power consumption can be significantly reduced. Recently, probabilistic CMOS and probabilistic Boolean circuits (PBCs) have been proposed to deal with power consumption issue. However, to the best of our knowledge, no correctness analysis and power optimization algorithms have been proposed for PBCs. Thus, in this paper, we first propose a statistical approach for evaluating the correctness of PBCs. Then, we propose strategies for power optimization of PBCs. Finally, we integrate these strategies with the correctness analysis as a power optimization algorithm for PBCs. The experimental results show that the proposed correctness analysis method is highly efficient and accurate, and that the power optimization algorithm saves 36% of total power-delay-product on average under a correctness constraint of 90% on a set of International Workshop on Logic and Synthesis (IWLS) 2005 benchmarks.
Year
DOI
Venue
2015
10.1109/TCAD.2015.2394378
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
international workshop on logic and synthesis,error resilient applications,network synthesis,boolean functions,Analysis,power optimization,image processing,circuit designs,statistical analysis,International Workshop on Logic and Synthesis,power delay product,analysis,statistical approach,probabilistic Boolean circuits,low-power design,correctness analysis,logic synthesis,probabilistic boolean circuits,synthesis for low power,Boolean functions
Journal
34
Issue
ISSN
Citations 
4
0278-0070
1
PageRank 
References 
Authors
0.37
13
6
Name
Order
Citations
PageRank
Ching-Yi Huang15810.06
Zheng-Shan Yu210.37
Yung-Chun Hu310.37
Tung-Chen Tsou410.37
Wang Chun-Yao525136.08
Yung-Chih Chen641339.89