Title
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS
Abstract
In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study.
Year
DOI
Venue
2015
10.1109/JSSC.2015.2408332
J. Solid-State Circuits
Keywords
Field
DocType
energy-quality tradeoff,error-free,ultra-low power processing,resiliency,sram,error-tolerant,approximate computing,near-threshold,boosting,temperature measurement,degradation,bit error rate,decoding,error correcting code
Computer science,Efficient energy use,Voltage,Static random-access memory,CMOS,Electronic engineering,Error detection and correction,Video decoder,Quality management,Bit error rate
Journal
Volume
Issue
ISSN
50
5
0018-9200
Citations 
PageRank 
References 
8
0.54
21
Authors
5
Name
Order
Citations
PageRank
Fabio Frustaci112917.55
Mahmood Khayatzadeh2493.53
David Blaauw38916823.47
Dennis Sylvester45295535.53
Massimo Alioto570688.98