Name
Abstract | ||
|---|---|---|
This brief deals with a new design of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. The proposed approach synergistically adopts the poly biasing technique in conjunction with single-well/flip-well configurations and body biasing to opportunely tune the threshold voltage of the devices in the standby and active mode. A tuning methodology is described to optimize the static energy consumption. Post-layout simulations, done at power supply voltages ranging between 1 V and 0.5 V, have shown that, in comparison with the state-of-the-art techniques based on the same UTBB FDSOI technology, the proposed design achieves a maximum leakage up to 85% lower without paying significant delay penalties. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TVLSI.2014.2384007 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
body biasing,sram peripheral,leakage optimization,poly biasing,ultrathin body and buried oxide (utbb) fully depleted silicon-on-insulator (fdsoi).,very large scale integration,transistors | Leakage (electronics),Computer science,Voltage,Static random-access memory,Electronic engineering,Ranging,Transistor,Threshold voltage,Very-large-scale integration,Electrical engineering,Biasing | Journal |
Volume | Issue | ISSN |
PP | 99 | 1063-8210 |
Citations | PageRank | References |
5 | 0.50 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pasquale Corsonello | 1 | 278 | 38.06 |
| Fabio Frustaci | 2 | 129 | 17.55 |
| Stefania Perri | 3 | 264 | 33.11 |