Paper Info
Title
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
Abstract
In this paper, the authors present a digital frequency-tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. This ensures robust operation of the ILCM across PVT variations even with a very narrow lock-in range (ΔFL<;500ppm) and enables its implementation using large N and high-Q LC DCO. The prototype ILCM generates an output clock in the range of 6.75 to 8.25GHz by multiplying FREF by 64 and achieves 190fsrms integrated jitter while consuming 2.25mW power. The timing diagram shown in the paper illustrates the basic principle behind the proposed FTL. Because reference injection leads to a diminished phase error, ΔΦ, even in the presence of FERR, we measure ΔΦ by disabling injection periodically. In the example shown in the paper, every 4th reference edge is not injected, which results in a larger ΔΦ that can be easily measured and used to correct FERR using a simple digital feedback loop as described next.
Year
DOI
Venue
2015
10.1109/ISSCC.2015.7062989
international solid-state circuits conference
Keywords
Field
DocType
CMOS integrated circuits,clocks,multiplying circuits,timing jitter,CMOS integrated circuit,all-digital continuous frequency-tracking loop,frequency 6.75 GHz to 8.25 GHz,injection locked clock multiplier,integrated jitter,integrated-jitter PVT,oscillator free running frequency,phase error,power 2.25 mW,size 65 nm,timing diagram
Phase-locked loop,Oscillation,Computer science,Control theory,Injection locking,Harmonic,Phase noise,CMOS,Electronic engineering,Jitter,CPU multiplier
Conference
Citations 
PageRank 
References 
5
0.72
5
Authors
4
Name
Order
Citations
PageRank
Ahmed Elkholy17716.19
Mrunmay Talegaonkar212315.61
Tejasvi Anand311016.98
Pavan Kumar Hanumolu455484.82