Title
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
Abstract
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18-μm CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.
Year
DOI
Venue
2016
10.1109/TVLSI.2015.2394459
VLSI) Systems, IEEE Transactions  
Keywords
Field
DocType
access speed,data retention time,embedded dram,gain cell,low power operation.,transistors,tin,vlsi
Dram,Computer science,Voltage,Electronic engineering,Static random-access memory,Real-time computing,eDRAM,Low voltage,Transistor,High voltage,Very-large-scale integration
Journal
Volume
Issue
ISSN
PP
99
1063-8210
Citations 
PageRank 
References 
6
0.59
6
Authors
6
Name
Order
Citations
PageRank
Robert Giterman1409.55
Adam Teman212919.12
Pascal Andreas Meinerzhagen3425.25
lior atias491.36
A. Burg51426126.54
Alexander Fish612321.24