Name
Abstract | ||
|---|---|---|
Thermal management becomes a huge challenge for modern IC designers, especially when chips go 3-D. Vertical slit field-effect transistor (VeSFET) technology provides an alternative thermal-friendly design choice. VeSFET-based chips not only have a much lower power density but also a better vertical thermal conductivity than their CMOS counterparts. For a VeSFET chip with ten stacked dies, the temperature increase is only 30% of that for CMOS-based chip. Assuming the same scaling trend for CMOS and VeSFET, VeSFET 3-D chips can postpone the appearance of dark silicon by three technology nodes compared with CMOS implementations. For VeSFET-based designs, different topologies of transistor arrays may result in different thermal behaviors. We perform thermal characterization of two-transistor array topologies. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TVLSI.2014.2325551 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
3-d,cmos,canvas,thermal,vertical slit field-effect transistor (vesfet),vertical slit field-effect transistor (vesfet).,transistors,thermal management,heating,thermal conductivity,silicon,field effect transistors,cmos integrated circuits,conductivity | Dark silicon,Transistor array,Thermal,Computer science,Thermal management of electronic devices and systems,Chip,Electronic engineering,CMOS,Transistor,Electrical engineering,Thermal conductivity | Journal |
Volume | Issue | ISSN |
23 | 5 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 15 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiang Qiu | 1 | 23 | 3.28 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| Wojciech Maly | 3 | 1976 | 352.57 |