Name
Title | ||
|---|---|---|
Multiple-Valued Fine-Grain Reconfigurable Vlsi Using A Global Tree Local X-Net Network |
Abstract | ||
|---|---|---|
A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each "X" intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1587/transinf.2013LOP0006 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
multiple-valued reconfigurable VLSI, fine-grain reconfigurable VLSI, global tree local X-net network, logic-in-memory architecture | Computer vision,Computer science,Theoretical computer science,Computational science,Artificial intelligence,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
E97D | 9 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xu Bai | 1 | 37 | 9.94 |
| Michitaka Kameyama | 2 | 431 | 99.93 |