Name
Abstract | ||
|---|---|---|
•Proposing a technique to mitigate the NBTI effect on both logic path and clock tree.•Focusing the asymmetric aging caused by NBTI on circuits using clock gating schemes.•Simultaneous usage of clock skew management, IVC and INC for aging mitigation.•Developing two optimization problems to increase the lifetime and reduce the area overhead.•Exploiting non-linear non-integer programing to solve the optimization problems. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1016/j.microrel.2014.09.033 | Microelectronics Reliability |
Keywords | Field | DocType |
Aging,NBTI,Clock skew,Lifetime,Optimization | Clock gating,Spice,NAND gate,Electronic engineering,Clock skew,Engineering,Electronic circuit,CPU multiplier,Optimization problem,Clock rate,Reliability engineering | Journal |
Volume | Issue | ISSN |
55 | 1 | 0026-2714 |
Citations | PageRank | References |
2 | 0.38 | 18 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Behzad Eghbalkhah | 1 | 5 | 1.11 |
| Mehdi Kamal | 2 | 189 | 30.41 |
| Ali Afzali-kusha | 3 | 365 | 54.65 |
| M. B. Ghaznavi-Ghoushchi | 4 | 31 | 14.57 |
| Massoud Pedram | 5 | 7801 | 1211.32 |