Title
FT-Matrix: A Coordination-Aware Architecture for Signal Processing
Abstract
Vector-SIMD architectures have gained increasing attention because of their high performance in signal-processing applications. However, the performance of existing vector-SIMD architectures remains limited because of their inefficiency in the coordinated exploitation of different hardware units. To solve this problem, this article proposes the FT-Matrix architecture, which improves the coordination of traditional vector-SIMD architectures from three aspects: the cooperation between the scalar and SIMD unit is refined with the dynamic coupling execution scheme, the communication among SIMD lanes is enhanced with the matrix-style communication, and data sharing among vector memory banks is accomplished by the unaligned vector memory accessing scheme. Evaluation results show an average performance gain of 58.5 percent against vector-SIMD architectures without the proposed improvements. A four-core chip with each core built on the FT-Matrix architecture is also under fabrication.
Year
DOI
Venue
2014
10.1109/MM.2013.129
IEEE Micro
Keywords
Field
DocType
simdu,signal processing,data communication,vector-simd architecture,coordination,vector-simd,scalar unit,vector memory accessing scheme,matrix algebra,matrix-style communication,dynamic coupling execution scheme,ft-matrix:,simd unit,su,coordination-aware architecture,data sharing,memory management,registers,kernel,hardware,vectors
Kernel (linear algebra),Memory bank,Signal processing,Architecture,Computer science,Data sharing,Parallel computing,SIMD,Chip,Memory management
Journal
Volume
Issue
ISSN
34
6
0272-1732
Citations 
PageRank 
References 
3
0.43
7
Authors
9
Name
Order
Citations
PageRank
Shuming Chen113838.21
Yaohua Wang24414.23
Sheng Liu374.06
Jiang-Hua Wan4155.86
Haiyan Chen541.52
Hengzhu Liu68623.28
Kai Zhang730.43
Xiang-Yuan Liu8112.45
Xi Ning943.15