Name
Title | ||
|---|---|---|
An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning |
Abstract | ||
|---|---|---|
Serial link transmitters which efficiently incorporate equalization, while also enabling fast power-state transitioning to leverage dynamic power scaling, are necessary to meet future systems' I/O requirements. This paper presents a scalable voltage-mode transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Topologies that allow for rapid power-up/down, including a replica-biased voltage regulator to power the output stages of multiple transmit channels and per-channel quadrature clock generation with injection-locked oscillators (ILO), enable fast power-state transitioning. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300 mV with up to 12 dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency and sub-3 ns power-up/down times. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2014.2353795 | J. Solid-State Circuits |
Keywords | Field | DocType |
cmos analogue integrated circuits,low static power dissipation,cmos process,power management,injection locked oscillators,per-channel quadrature clock generation,output eye quality,capacitance,driver circuits,system i/o requirements,scalable voltage-mode transmitter,low-power,size 65 nm,voltage 100 mv to 300 mv,transmit equalization,bit rate 8 gbit/s to 16 gbit/s,high-speed i/o,driver segmentation,transmitters,equalization,automatic phase calibration,voltage regulators,replica-biased voltage regulator,pre-driver complexity reduction,capacitively driven low-swing global clock distribution,data rates,global clock distribution network,injection-locked oscillators,timing error calibration,voltage-mode driver,injection-locked oscillator,dynamic power scaling,multiple transmit channels,clock distribution networks,equalisers,serial link transmitters,analog impedance modulation equalization,energy efficiency,analog tap control,power-state transitioning,impedance-modulated 2-tap equalizer,local ilo-generated quarter-rate clocks | Serial communication,Transmitter,Equalization (audio),Computer science,Voltage,Electronic engineering,Electrical impedance,Modulation,Dynamic demand,Electrical engineering,Voltage regulator | Journal |
Volume | Issue | ISSN |
49 | 11 | 0018-9200 |
Citations | PageRank | References |
5 | 0.53 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Hoon Song | 1 | 12 | 2.26 |
| Noah Hae-Woong Yang | 2 | 6 | 0.90 |
| Hao Li | 3 | 5 | 0.53 |
| Patrick Yin Chiang | 4 | 150 | 19.20 |
| Samuel Palermo | 5 | 46 | 7.88 |