Name
Abstract | ||
|---|---|---|
This paper presents the Scout Flip-Flop, a new performance Sensor for toleranCe and predictive detectiOn of delay-faUlTs in synchronous digital circuits. The sensor is based on a new master-slave Flip-Flop (FF), the Scout FF, with built-in functionality to locally (inside the FF) create two distinct guard-band windows: (1) a tolerance window, to increase tolerance to late transitions, making the Scout's master latch transparent during an additional predefined period after the clock trigger; and (2) a detection window, which starts before the clock edge trigger and persists during the tolerance window, to inform that performance and circuit functionality is at risk. When a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and a delay-fault may occur. Hence, the existence of a tolerance window, introduces an extra time-slack by borrowing time from subsequent clock cycles. Moreover, as the predictive-error detection window starts prior to the clock edge trigger, it provides an additional safety margin and may be used to trigger corrective actions before real error occurrence, such as clock frequency reduction. Both tolerance and detection windows are defined by design and are sensitive to performance errors, increasing its size in worst PVTA conditions. Extensive SPICE simulations allowed characterizing the new flip-flop and simulation results are presented for 65nm CMOS technology, using Berkeley Predictive Technology Models (PTM), showing Scout's effectiveness on tolerance and predictive error detection. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/DFT.2014.6962092 | Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
Keywords | Field | DocType |
CMOS logic circuits,delays,fault diagnosis,fault tolerance,flip-flops,integrated circuit reliability,Berkeley predictive technology models,CMOS technology,PVTA,SCOUT flip-flop,SPICE simulations,aging variation,delay fault detection,master-slave Flip-Flop,performance sensor,power supply voltage variation,predictive detection,predictive error detection,process variation,size 65 nm,synchronous digital circuit,temperature variation,tolerance detection,PVTA variations,Scout,aging sensor,delay-fault tolerance,performance sensor,predictive fault detection,time-borrowing | Digital electronics,Computer science,Spice,Voltage,Error detection and correction,Real-time computing,Electronic engineering,CMOS,Transistor,Signal edge,Clock rate | Conference |
Citations | PageRank | References |
1 | 0.36 | 18 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorge Semião | 1 | 57 | 12.11 |
| David Saraiva | 2 | 1 | 0.36 |
| Carlos Leong | 3 | 8 | 3.65 |
| André Romão | 4 | 1 | 0.36 |
| Marcelino B. Santos | 5 | 129 | 20.76 |
| Isabel C. Teixeira | 6 | 42 | 8.70 |
| João Paulo Teixeira | 7 | 62 | 7.09 |
| Semiao, J. | 8 | 1 | 0.36 |
| Romao, A. | 9 | 1 | 0.36 |