Name
Title | ||
|---|---|---|
Half-DRAM: a high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation |
Abstract | ||
|---|---|---|
DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1, 2] has been proposed to reduce the activation/ precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead. In this paper, we propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enable only half of a row being activated. The half-row activation can effectively reduce activation power and meanwhile sustain the full bandwidth one bank can provide. In addition, the half-row activation in Half-DRAM relaxes the power constraint in DRAM, and opens up opportunities for further performance gain. Furthermore, two half-row accesses can be issued in parallel by integrating the sub-array level parallelism to improve the memory level parallelism. The experimental results show that Half-DRAM can achieve both significant performance improvement and power reduction, with negligible design overhead
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Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCA.2014.6853217 | ISCA |
Keywords | Field | DocType |
decoding,memory level parallelism,bandwidth,computer architecture,degradation | Sense amplifier,Dram,Registered memory,Computer science,Parallel computing,Static random-access memory,Universal memory,Real-time computing,Memory controller,Memory rank,CAS latency | Conference |
ISSN | ISBN | Citations |
1063-6897 | 978-1-4799-4394-4 | 33 |
PageRank | References | Authors |
1.05 | 22 | 6 |