Paper Info
Title
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips
Abstract
Last level cache (LLC) is crucial for the performance of chip multiprocessors (CMPs), while power is a significant design concern for 3D CMPs. In this paper, we focus on the SRAM-based Non-Uniform Cache Architecture (NUCA) for 3D Multi-core Network-on-Chip (McNoC) systems. A tightly mixed SRAM NUCA for 3D mesh NoC is presented and analyzed. We evaluate the performance and network power with benchmarks based on a full system simulation framework. Experiment results on 16-core 3D NoC systems show that the tightly mixed NUCA could provide up to 31.71% and on average 5.95% performance improvement compared to a base 3D NUCA scheme. The tightly mixed 3D NUCA NoC can reduce network power consumption in 1.07%-15.74% and 9.64% on average compared to a baseline 3D NoCs. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with stacking NUCA.
Year
DOI
Venue
2014
10.1109/ISCAS.2014.6865546
ISCAS
Keywords
Field
DocType
llc,3d mesh noc,3d mcnoc systems,cache storage,multi-core,network power evaluation,3d cmp,last level cache,sram chips,sram nuca,3d multicore network on chips,multiprocessing systems,nuca,chip multiprocessors,noc,network power consumption,network-on-chip,3d chip,full system simulation framework,sram-based nonuniform cache architecture,network on chip,benchmark testing,stacking,multi core,multicore processing
Network on,Computer architecture,Computer science,Cache,Cache-only memory architecture,Static random-access memory,Chip,Multi-core processor,Performance improvement,Power consumption
Conference
ISSN
Citations 
PageRank 
0271-4302
1
0.35
References 
Authors
0
6
Name
Order
Citations
PageRank
Yuang Zhang182.17
Li Li 00032164.79
Zhonghai Lu31063100.12
Axel Jantsch41875169.83
Yuxiang Fu5115.65
Minglun Gao610312.19