Name
Abstract | ||
|---|---|---|
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by reintroducing more complex in-ring buffering and buffered flow control. Our goal in this paper is to design a new hierarchical ring interconnect that can maintain most of the simplicity of traditional ring designs (i.e., no in-ring buffering or buffered flow control) while achieving high scalability as more complex buffered hierarchical ring designs. To this end, we revisit the concept of a hierarchical-ring networkon-chip. Our design, called HiRD (Hierarchical Rings with Deflection), includes critical features that enable us to mostly maintain the simplicity of traditional simple ring topologies while providing higher energy efficiency and scalability. First, HiRD does not have any buffering or buffered flow control within individual rings, and requires only a small amount of buffering between the ring hierarchy levels. When inter-ring buffers are full, our design simply deflects flits so that they circle the ring and try again, which eliminates the need for in-ring buffering. Second, we introduce two simple mechanisms that together provide an end-to-end delivery guarantee within the entire network (despite any deflections that occur) without impacting the critical path or latency of the vast majority of network traffic. Our experimental evaluations on a wide variety of multiprogrammed and multithreaded workloads and synthetic traffic patterns show that HiRD attains equal or better performance at better energy efficiency than multiple versions of both a previous hierarchical ring design and a traditional single ring design. We also extensively analyze our design's characteristics and injection and delivery guarantees. We conclude that HiRD can be a compelling design point that allows higher energy efficiency and scalability while retaining the simplicity and appeal of conventional ring-based designs. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/SBAC-PAD.2014.31 | SBAC-PAD |
Keywords | Field | DocType |
buffer circuits,integrated circuit interconnections,multi-threading,multiprocessor interconnection networks,network routing,network topology,network-on-chip,HiRD,buffered flow control,complex buffered hierarchical ring design,deflection routing,end-to-end delivery guarantee,energy efficiency,hierarchical ring interconnect,hierarchical ring network,hierarchical rings with deflection,hierarchical-ring network-on-chip,in-ring buffering,inter-ring buffer,multiprogrammed workload,multithreaded workload,ring hierarchy level,ring interconnects,ring topology,single ring design,synthetic traffic pattern | Computer science,Computer network,Real-time computing,Distributed computing,Simple ring,Efficient energy use,Hierarchical routing,Parallel computing,Network topology,Deflection routing,Critical path method,Ring network,Scalability | Conference |
ISSN | Citations | PageRank |
1550-6533 | 10 | 0.52 |
References | Authors | |
30 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rachata Ausavarungnirun | 1 | 780 | 29.88 |
| Chris Fallin | 2 | 741 | 20.86 |
| Xiangyao Yu | 3 | 270 | 16.17 |
| Kai-Wei Chang | 4 | 4735 | 276.81 |
| Greg Nazario | 5 | 55 | 2.41 |
| Reetuparna Das | 6 | 1117 | 47.07 |
| Gabriel H. Loh | 7 | 2481 | 134.10 |
| Onur Mutlu | 8 | 9446 | 357.40 |