Name
Abstract | ||
|---|---|---|
As DRAM density keeps increasing, more rows need to be protected in a single refresh with the constant refresh number. Since no memory access is allowed during a refresh, the refresh penalty is no longer trivial and can result in significant performance degradation. To mitigate the refresh penalty, a Concurrent-REfresh-Aware Memory system (CREAM) is proposed in this work so that memory access and refresh can be served in parallel. The proposed CREAM architecture distinguishes itself with the following key contributions: (1) Under a given DRAM power budget, sub-rank-level refresh (SRLR) is developed to reduce refresh power and the saved power is used to enable concurrent memory access; (2) sub-array-level refresh (SALR) is also devised to effectively lower the probability of the conflict between memory access and refresh; (3) In addition, novel sub-array level refresh scheduling schemes, such as sub-array round-robin and dynamic scheduling, are designed to further improve the performance. A quasi-ROR interface protocol is proposed so that CREAM is fully compatible with JEDEC-DDR standard with negligible hardware overhead and no extra pin-out. The experimental results show that CREAM can improve the performance by 12.9% and 7.1% over the conventional DRAM and the Elastic-Refresh DRAM memory, respectively. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/HPCA.2014.6835947 | HPCA |
Keywords | Field | DocType |
processor scheduling,dynamic scheduling,subarray round-robin,dram density,jedec-ddr standard,srlr,cream architecture,dram power budget,dram chips,subrank-level refresh,subarray-level refresh,refresh penalty,quasiror interface protocol,memory architecture,concurrent-refresh-aware dram memory architecture,concurrent memory access,subarray level refresh scheduling schemes,hardware overhead,memory refresh,concurrent-refresh-aware memory system,salr,probability,elastic-refresh dram memory,degradation,erbium | Dram,Power budget,Architecture,Interface protocol,Scheduling (computing),Computer science,Parallel computing,Dram memory,Real-time computing,Dynamic priority scheduling,Memory refresh,Embedded system | Conference |
ISSN | Citations | PageRank |
1530-0897 | 16 | 0.65 |
References | Authors | |
13 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tao Zhang | 1 | 402 | 19.22 |
| Matthew Poremba | 2 | 78 | 5.46 |
| Cong Xu | 3 | 1154 | 48.25 |
| Guangyu Sun | 4 | 1920 | 111.55 |
| Yuan Xie | 5 | 6430 | 407.00 |