Name
Abstract | ||
|---|---|---|
In this work, a multi-path Trace-Back Viterbi decoder architecture is proposed. It offers almost ideal error correction quality with relatively low overhead. Moreover, a technique that enhances the error correction quality of Register-Exchange decoders as well as a normalization technique that saves considerable area are introduced. The proposed techniques can be utilized for efficient realizations of high speed systolic as well as low speed sequential Vioterbi decoder architectures. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICECS.2003.1301718 | ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 |
Keywords | DocType | Citations |
error correction,viterbi decoding,sequential circuits,viterbi decoder | Conference | 3 |
PageRank | References | Authors |
0.45 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdulfattah Mohammad Obeid | 1 | 14 | 7.26 |
| Alberto García-Ortiz | 2 | 66 | 19.23 |
| Mihail Petrov | 3 | 37 | 5.69 |
| Manfred Glesner | 4 | 1121 | 255.04 |