Paper Info
Title
Closed-loop simulation method for evaluation of static offset in discrete-time comparators
Abstract
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.
Year
DOI
Venue
2014
10.1109/ICECS.2014.7050041
Electronics, Circuits and Systems
Keywords
Field
DocType
CMOS analogue integrated circuits,comparators (circuits),discrete time systems,integrated circuit modelling,CMOS technology,closed-loop algorithm,closed-loop simulation method,discrete-time comparators,realistic behavioral models,size 0.18 mum,static offset evaluation,transistor-level simulations,Flash-ADC,comparator offset evaluation,discrete-time,simulation-based techniques
Orders of magnitude (numbers),Closed loop simulation,Comparator,Computer science,CMOS,Flash ADC,Electronic engineering,Discrete time and continuous time,Offset (computer science)
Conference
Citations 
PageRank 
References 
0
0.34
3
Authors
4
Name
Order
Citations
PageRank
Antonio J. Ginés1177.43
Eduardo J. Peralías25816.71
Gildas Leger3519.99
Adoración Rueda427540.01