Name
Abstract | ||
|---|---|---|
This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/MIXDES.2014.6872168 | MIXDES |
Keywords | Field | DocType |
cmos digital integrated circuits,current-mode circuits,low-pass filters,sigma-delta modulation,adc,cmos technology,sndr,bandwidth 2 mhz,dynamic range,electrical simulation,frequency 400 mhz,hybrid current-mode passive second-order continuous-time σδ modulator,low-pass passive filter topology,power 132 muw,power consumption,sigma-delta modulator,signal-to-noise-plus-distortion ratio,single continuous-time current-mode integrator,size 65 nm,voltage 1.2 v,current-mode,sigma delta modulator,frequency modulation,low pass filters,cmos integrated circuits | Electronic filter,Dynamic range,Computer science,Integrator,Modulation,Electronic engineering,CMOS,Delta-sigma modulation,Bandwidth (signal processing),Electrical engineering,Clock rate | Conference |
Citations | PageRank | References |
1 | 0.36 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pawel Sniatala | 1 | 17 | 4.54 |
| Mariusz Naumowicz | 2 | 7 | 1.83 |
| de Melo, J.L.A. | 3 | 1 | 0.70 |
| Nuno F. Paulino | 4 | 72 | 24.92 |
| João Goes | 5 | 88 | 27.95 |