Name
Abstract | ||
|---|---|---|
A Freeze Vernier delay line time-to-digital converter for very low power and high resolution is presented. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the start line can be frozen by the stop line, omitting the power-hungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with additional circuitry. The TDC core consists of inverters and current-enabled inverters only. A proof-of-concept design has been implemented in 65nm CMOS with a typical resolution of 4.88ps, a dynamic energy consumption of 106.22fJ per conversion and a combined gate width of 96μm. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISCAS.2014.6865071 | Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,convertors,delay lines,integrated circuit design,invertors,CMOS,D-registers,Freeze Vernier delay line time-to-digital converter,current-enabled inverters,delay lines,dynamic energy consumption,energy 0.1 pJ,energy 106.22 pJ,power-hungry time capture elements,proof-of-concept design,size 65 nm,size 96 mum,time 4.88 ps | Computer science,Vernier scale,Electronic engineering,CMOS,Dynamic energy,Electrical engineering,Time-to-digital converter | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kristof Blutman | 1 | 0 | 0.34 |
| Angevare, J. | 2 | 0 | 0.34 |
| Amir Zjajo | 3 | 57 | 20.08 |
| Nick van der Meijs | 4 | 30 | 7.49 |