Abstract | ||
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This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability, mean time to failure (MTTF) and area overhead with existing works. For a 10 × 10 mesh, it gives a 1.14 reliability gain over quad-spare mesh, 1.42 reliability gain over column-spare mesh and 21.195 reliability gain over normal mesh. The mean time to failure (MTTF) gains over column-spare, quad spare and normal mesh are 3.19, 7.51, and 33.38 respectively. We have also presented a system performance report which includes throughput and latency of the proposed design. |
Year | DOI | Venue |
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2014 | 10.1109/ISCAS.2014.6865545 | Circuits and Systems |
Keywords | DocType | ISSN |
network routing,network topology,network-on-chip,MTTF,NoC,mean time to failure,network-on-chip design,router redundancy,routing algorithm,Fault Tolerance,Network-on-Chip,Reconfigurable,Spare Router | Conference | 0271-4302 |
Citations | PageRank | References |
7 | 0.47 | 11 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
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Navonil Chatterjee | 1 | 26 | 6.21 |
Santanu Chattopadhyay | 2 | 343 | 44.89 |
Kanchan Manna | 3 | 44 | 5.53 |