Name
Title | ||
|---|---|---|
Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion |
Abstract | ||
|---|---|---|
This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADC's. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that, reducing the supply voltage does not necessarily increases the used energy per conversion. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1009992 | Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium |
Keywords | Field | DocType |
analogue-digital conversion,circuit optimisation,clocks,genetic algorithms,integrated circuit design,low-power electronics,pipeline processing,1 pJ,1.5 V,10 bit,CMOS,clock-boosting techniques,genetic algorithms,low-voltage pipelined ADCs,multi-bit architectures,optimization methodology,power efficiency,supply voltage,switched-opamp techniques | Electrical efficiency,Flight dynamics (spacecraft),Low voltage cmos,Computer science,Voltage,Electronic engineering,Integrated circuit design,Genetic algorithm,Low-power electronics,Joule | Conference |
Volume | Citations | PageRank |
1 | 5 | 0.97 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vaz, B. | 1 | 5 | 0.97 |
| Nuno F. Paulino | 2 | 72 | 24.92 |
| João Goes | 3 | 88 | 27.95 |
| Costa, R. | 4 | 14 | 2.26 |