Name
Abstract | ||
|---|---|---|
In this paper we present a local strategy for sizing CMOS circuits. We show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed / area performances are given for a linear matrix style layout implementation. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/EDAC.1991.206368 | EURO-DAC |
Keywords | Field | DocType |
sizing CMOS circuit,area optimal,area performance,linear matrix style layout,NAND gate,adder cell,direct comparison,explicit definition,initial electrical netlist,irregular inverter array,formal sizing rule | Inverter,Netlist,Adder,AND-OR-Invert,Computer science,Electronic engineering,CMOS,Sizing,NAND logic,Electronic circuit | Conference |
ISBN | Citations | PageRank |
0-8186-2130-3 | 7 | 0.99 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Auvergne | 1 | 145 | 31.67 |
| N. Azemard | 2 | 104 | 14.17 |
| Bonzom, V. | 3 | 8 | 1.66 |
| Denis Deschacht | 4 | 19 | 5.91 |
| Michel Robert | 5 | 7 | 0.99 |