Title
Regularization of hierarchical VHDL-AMS models using bipartite graphs
Abstract
The powerful capability of VHDL-AMS to describe complex continuous systems in form of differential algebraic equations (DAEs) often leads to problems during numerical simulation. This paper presents a discrete algorithm to analyze unsolvable DAE systems and to correct the underlying hierarchical VHDL-AMS description automatically in interaction with the designer, avoiding time-consuming manual error correction.
Year
DOI
Venue
2002
10.1109/DAC.2002.1012685
DAC
Keywords
Field
DocType
VLSI,circuit simulation,differential equations,graph theory,hardware description languages,integrated circuit design,mixed analogue-digital integrated circuits,analog design,bipartite graphs,complex continuous systems,differential algebraic equations,discrete algorithm,hierarchical VHDL-AMS models,numerical simulation,regularization,unsolvable DAE systems
Graph theory,Differential equation,Algorithm design,Computer science,Bipartite graph,Algorithm,Theoretical computer science,Electronic engineering,Error detection and correction,Differential algebraic equation,VHDL-AMS,Hardware description language
Conference
ISSN
ISBN
Citations 
0738-100X
1-58113-461-4
3
PageRank 
References 
Authors
1.00
2
2
Name
Order
Citations
PageRank
Jochen Mades132.35
Manfred Glesner21121255.04