Name
Abstract | ||
|---|---|---|
In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TEST.2002.1041815 | ITC |
Keywords | Field | DocType |
VLSI,automatic testing,boundary scan testing,integrated circuit testing,logic testing,standardisation,system-on-chip,Philips system chips,area-cost evaluation,core-based debug architecture,core-based design,core-based scan architecture,core-based test,scan-based debug,silicon debug | Architecture,System on a chip,Computer science,System testing,Electronic engineering,Background debug mode interface,Time to market,Very-large-scale integration,Chip-scale package,Embedded system,Debugging | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7542-4 | 52 |
PageRank | References | Authors |
3.54 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bart Vermeulen | 1 | 142 | 13.81 |
| Tom Waayers | 2 | 128 | 11.47 |
| Sandeep Kumar Goel | 3 | 710 | 46.49 |