Name
Abstract | ||
|---|---|---|
This paper presents a new low-power high-speed fully static CMOS variable-time adder. The VLSI implementation proposed here is based on the statistical carry look-ahead addition technique. The new circuit takes advantage of an innovative way of using a composition of propagate signals and of appropriately designed overlapped execution modules to reduce average addition time, layout area, and power dissipation. A 56-bit adder designed as described here and realized using AMS 0.35-/spl mu/m CMOS standard cells at 3.3V supply voltage shows an average addition time of about 4.3 ns and a maximum power dissipation of only 50 mW at 200-MHz repetitive frequency using a silicon area of less than 0.23 mm/sup 2/. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TVLSI.2002.801567 | VLSI) Systems, IEEE Transactions |
Keywords | DocType | Volume |
CMOS logic circuits,VLSI,adders,carry logic,high-speed integrated circuits,integrated circuit layout,logic CAD,low-power electronics,0.35 micron,200 MHz,3.3 V,4.3 ns,50 mW,56 bit,VLSI,average addition time,fully static CMOS variable-time adder,high-speed asynchronous addition,layout area,overlapped execution modules,power dissipation,propagate signals,repetitive frequency,statistical carry look-ahead addition technique | Journal | 10 |
Issue | ISSN | Citations |
5 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefania Perri | 1 | 264 | 33.11 |
| P. Corsonello | 2 | 50 | 5.31 |
| Giuseppe Cocorullo | 3 | 106 | 17.00 |