Name
Title | ||
|---|---|---|
Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver |
Abstract | ||
|---|---|---|
This paper presents a digitally programmable delay line intended for use as a timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ISCAS.2003.1205518 | Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium |
Keywords | Field | DocType |
circuit simulation,delay lines,delay lock loops,network synthesis,programmable circuits,radar receivers,sigma-delta modulation,timing circuits,timing jitter,ΣΔ modulator,11 bit,RADAR ranging system,delay-locked loop,digitally programmable DLL,jitter noise filter,low-cost radar receiver,output clock,programmable delay line,timing generator resolution,ultra wide band radar receiver | Delay calculation,Radar,Delay line oscillator,Computer science,Delay-locked loop,Group delay and phase delay,Digital delay line,Electronic engineering,Jitter,Matched filter | Conference |
Volume | ISBN | Citations |
1 | 0-7803-7761-3 | 1 |
PageRank | References | Authors |
0.40 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nuno F. Paulino | 1 | 72 | 24.92 |
| Serrazina, M. | 2 | 1 | 0.40 |
| João Goes | 3 | 88 | 27.95 |
| Adolfo Steiger-Garcao | 4 | 166 | 11.37 |