Name
Title | ||
|---|---|---|
A compact VLSI design for recursive neural networks with hardware annealing capability |
Abstract | ||
|---|---|---|
In this paper, we present a compact CMOS VLSI design for recursive neural networks with the capability of hardware annealing. Locally-connected recursive neural networks are a class of analog nonlinear networks which can solve many important optimization, and signal processing problems and is suitable for VLSI implementation because of its low demand on inter-cell connections. Hardware annealing, which is a paralleled version of effective mean-field annealing in analog networks, is a highly-efficient method to find global optimal solutions of recursive neural networks. A two-neuron prototype chip to demonstrate the functionality of hardware annealing is designed, analyzed and implemented in 2.0 μm CMOS technology using mixed-signal design methodology through MOSIS. For circuit reliability and compactness, a unit current of 6 μA is used. The cell density is 505 cells/cm2 and the cell time constant time is designed to be 0.3 μs. Laboratory experimental results to show the behavior of this two neuron chip was produced with annealing control signals from a function generator |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ICNN.1995.488866 | Neural Networks, 1995. Proceedings., IEEE International Conference |
Keywords | Field | DocType |
cmos analogue integrated circuits,vlsi,analogue multipliers,analogue processing circuits,circuit optimisation,neural chips,simulated annealing,0.3 mus,2 mum,6 mua,mosis,analog nonlinear networks,cell density 505 cells/cm2,circuit reliability,compact cmos vlsi design,compactness,effective mean-field annealing,hardware annealing capability,inter-cell connections,locally-connected recursive neural networks,mixed-signal design methodology,optimization,signal processing,vlsi design,chip,time constant,global optimization,design methodology | Simulated annealing,Signal processing,Function generator,Computer science,Circuit reliability,Chip,CMOS,Artificial neural network,Computer hardware,Very-large-scale integration | Conference |
Volume | ISBN | Citations |
4 | 0-7803-2768-3 | 0 |
PageRank | References | Authors |
0.34 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chou, E.Y. | 1 | 1 | 0.71 |
| B. J. Sheu | 2 | 129 | 28.40 |
| S. H. Jen | 3 | 2 | 1.93 |