Name
Abstract | ||
|---|---|---|
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EDTC.1996.494153 | EDTC '96 Proceedings of the 1996 European conference on Design and Test |
Keywords | Field | DocType |
cmos logic circuits,buffer circuits,delays,integrated circuit design,logic design,cmos buffers,spice simulations,buffer design,buffer insertion limit,buffer selection,explicit delay modeling,minimum power-delay product,power dissipation,standard cell library,two stage inverter arrays | Logic synthesis,Inverter,Power–delay product,Propagation delay,Spice,Semiconductor device modeling,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,Standard cell | Conference |
ISSN | ISBN | Citations |
1066-1409 | 0-8186-7424-5 | 12 |
PageRank | References | Authors |
1.91 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Turgis | 1 | 42 | 6.61 |
| N. Azemard | 2 | 104 | 14.17 |
| Daniel Auvergne | 3 | 145 | 31.67 |