Name
Abstract | ||
|---|---|---|
This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Traditional notions of a spot defect and local and global pro- cess variations are analyzed and their shortcomings are exposed. A detailed taxonomy of process-induced deforma- tions of DSM IC structures, enabling modeling and charac- terization of IC malfunctions, is proposed. The blueprint of a roadmap enabling such a characterization is suggested. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/TEST.2003.1271071 | Test Conference, 2003. Proceedings. ITC 2003. International |
Keywords | Field | DocType |
defect characterization.,diagno- sis,fault modeling,: yield learning,defects,integrated circuit layout,taxonomy,geometry,fault model,boolean algebra | Prime (order theory),Integrated circuit layout,Existential quantification,Computer science,IC layout editor,Electronic engineering,Blueprint,Boolean algebra,Physical design,Integrated circuit development | Conference |
Volume | ISSN | ISBN |
1 | 1089-3539 | 0-7803-8106-8 |
Citations | PageRank | References |
23 | 1.41 | 28 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wojciech Maly | 1 | 1976 | 352.57 |
| Gattiker, A. | 2 | 23 | 1.41 |
| T. Zanon | 3 | 35 | 2.58 |
| Vogels, T. | 4 | 23 | 1.41 |