Paper Info
Title
PBExplore: a framework for compiler-in-the-loop exploration of partial bypassing in embedded processors
Abstract
Varying partial bypassing in pipelined processors is an effective way to make performance, area and energy trade-offs in embedded processors. However, performance evaluation of partial bypassing in processors has been inaccurate, largely due to the absence of bypass-sensitive retargetable compilation techniques. Furthermore no existing partial bypass exploration framework estimates the power and cost overhead of partial bypassing. In this paper we present PBExplore: A framework for Compiler-in-the-Loop exploration of partial bypassing in processors. PBExplore accurately evaluates the performance of a partially by-passed processor using a generic bypass-sensitive compilation technique. It synthesizes the bypass control logic and estimates the area and energy overhead of each bypass configuration. PBExplore is thus able to effectively perform multi-dimensional exploration of the partial bypass design space. We present experimental results on the Intel XScale architecture on MiBench benchmarks and demonstrate the need, utility and exploration capabilities of PBExplore.
Year
DOI
Venue
2005
10.1109/DATE.2005.236
DATE
Keywords
Field
DocType
embedded systems,microprocessor chips,performance evaluation,program compilers,Intel XScale architecture,MiBench benchmarks,PBExplore,bypass control logic,compiler-in-the-loop exploration,embedded processors,generic bypass-sensitive compilation,multidimensional exploration,partial bypassing,performance evaluation
Design space,Application specific,Architecture,Computer science,Parallel computing,Compiler,Real-time computing,SystemC,Control logic,Crossbar switch,Embedded system
Conference
ISSN
ISBN
Citations 
1530-1591
0-7695-2288-2
12
PageRank 
References 
Authors
0.78
6
4
Name
Order
Citations
PageRank
Aviral Shrivastava181268.67
Nikil Dutt24960421.49
Alexandru Nicolau32265307.74
Eugene Earlie4775.23