Name
Abstract | ||
|---|---|---|
This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2n. Third, it is shown that the complete circuit, i.e. a m×m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2n test configurations using the XOR tree and shift register structures |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ATS.1998.741623 | Asian Test Symposium |
Keywords | Field | DocType |
fault diagnosis,field programmable gate arrays,integrated circuit interconnections,integrated circuit testing,logic testing,multiplexing equipment,shift registers,CIMs,SRAM-based FPGA,XOR tree,configurable interface modules,functional fault model,interconnect/logic interface test,logic cell,logic cells,multiplexers,shift register structures,stuck-at fault model,test configurations | Shift register,Logic gate,Computer science,Logic optimization,Programmable logic array,Field-programmable gate array,Static random-access memory,Real-time computing,Multiplexer,Electronic engineering,Logic family | Conference |
ISSN | ISBN | Citations |
1081-7735 | 0-8186-8277-9 | 4 |
PageRank | References | Authors |
0.50 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Renovell | 1 | 224 | 18.93 |
| J. M. Portal | 2 | 176 | 20.95 |
| J. Figueras | 3 | 227 | 19.91 |
| Y. Zorian | 4 | 499 | 47.97 |