Paper Info
Title
Systematic power-performance trade-off in MPEG-4 by means of selective function inlining steered by address optimisation opportunities
Abstract
The hierarchical structure of real-life data dominated applications limits the exploration space for high level optimisations. This limitation is often overcome by function inlining. However, it increases the basic block code size, which causes a significant growth of instruction cache misses and thus performance slow-down. This effect has been confirmed on experiments with our applications. We have developed a novel methodology for selective function inlining steered by cost/gain balance to trade-off power and performance. Although this results in a speed up, the increase of the instruction cache misses is still present, i.e. the memory power consumption is higher This implies the possibility of the Pareto-optimal trade-offs between memory power and performance. Our methodology is demonstrated on an MPEG-4 video decoder
Year
DOI
Venue
2002
10.1109/DATE.2002.998435
Paris
Keywords
Field
DocType
block codes,cache storage,decoding,low-power electronics,video signal processing,MPEG-4,Pareto-optimal trade-offs,address optimisation opportunities,basic block code size,cost/gain balance,exploration space,hierarchical structure,instruction cache misses,memory power,memory power consumption,performance slow-down,selective function inlining,systematic power-performance trade-off,video decoder
Cache,Computer science,Parallel computing,Block code,Real-time computing,Basic block,Decoding methods,MPEG-4,Video decoder,Speedup,Low-power electronics
Conference
ISSN
ISBN
Citations 
1530-1591
0-7695-1471-5
2
PageRank 
References 
Authors
0.38
11
3
Name
Order
Citations
PageRank
Martin Palkovic121316.11
M. Miranda214411.00
F. Catthoor389783.95