Name
Abstract | ||
|---|---|---|
A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop filter to the voltage controlled oscillator and achieves low jit- ter performance. Test chip fabricated in a 0.13µm CMOS process achieves BER < 10−12, ±1500ppm lock-in range, ±2500ppm tracking range, recovered clock jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps. I. INTRODUCTION The ever increasing demand for large off-chip I/O band- width requires integration of many serial links on a large digital chip. These serial links need to be low-power, easily portable to different process technologies, and should operate reliably in noisy environments. A clock and data recovery (CDR) circuit is an integral component of these serial links and is the focus of this paper. Modern CDRs are commonly imple- mented using analog phase-locked loops (PLLs) as shown in Fig. 1 (1). A bang-bang phase detector (!!PD) determines sign |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/CICC.2006.320829 | San Jose, CA |
Keywords | Field | DocType |
CMOS digital integrated circuits,analogue-digital conversion,clocks,jitter,0.13 micron,1.2 V,1.6 Gbit/s,12 mW,CMOS process,digital clock and data recovery circuit,digital loop filter,digital-to-analog converters,low jitter performance,voltage controlled oscillator | Computer science,Delay-locked loop,Clock domain crossing,Electronic engineering,Clock skew,Synchronous circuit,Digital clock,Digital clock manager,Jitter,Time-to-digital converter | Conference |
ISBN | Citations | PageRank |
1-4244-0076-7 | 7 | 1.08 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pavan Kumar Hanumolu | 1 | 240 | 27.03 |
| Min-Gyu Kim | 2 | 76 | 15.90 |
| Gu-Yeon Wei | 3 | 1927 | 214.15 |
| Un-Ku Moon | 4 | 836 | 140.98 |