Name
Title | ||
|---|---|---|
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers |
Abstract | ||
|---|---|---|
Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCSII.2007.906086 | Circuits and Systems II: Express Briefs, IEEE Transactions |
Keywords | Field | DocType |
CMOS analogue integrated circuits,circuit simulation,network synthesis,operational amplifiers,CMOS voltage follower,circuital simulations,operational amplifiers,settling time minimization,size 0.35 mum,three-stage nested-Miller amplifiers,Analog design,frequency compensation,operational amplifiers (op-amps),transient response | Transient response,Step response,Control theory,Settling time,Buffer amplifier,Electronic engineering,CMOS,Frequency compensation,Mathematics,Operational amplifier,Amplifier | Journal |
Volume | Issue | ISSN |
55 | 1 | 1549-7747 |
Citations | PageRank | References |
16 | 0.87 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Pugliese | 1 | 115 | 12.90 |
| Gregorio Cappuccino | 2 | 36 | 10.11 |
| Giuseppe Cocorullo | 3 | 106 | 17.00 |