Name
Abstract | ||
|---|---|---|
180 Kbit magnetoresistive random access memory (MRAM) designed for embedding in a 0.28 micron CMOS process has been developed. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell. The architecture, write driver, and sense amplifier are described. The use of a test register to characterize and optimize the memory design is also discussed. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/CICC.2007.4405848 | San Jose, CA |
Keywords | Field | DocType |
cmos memory circuits,magnetic tunnelling,magnetoresistive devices,random-access storage,cmos process,mram memory module,magnetic tunnel junction,magnetoresistive random access memory,size 0.28 micron,storage capacity 181 kbit,mram,magnetoresistance,pass transistor,cmos,switched capacitor,cmos integrated circuits | Sense amplifier,Dirty bit,Computer science,Bit field,Electronic engineering,Magnetoresistive random-access memory,Bit array,Bit manipulation,Electrical engineering,Memory architecture,Bit cell | Journal |
Volume | Issue | ISBN |
43 | 8 | 978-1-4244-1623-3 |
Citations | PageRank | References |
1 | 0.75 | 2 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joseph Nahas | 1 | 68 | 21.60 |
| Thomas W. Andre | 2 | 2 | 1.18 |
| bradley j garni | 3 | 1 | 0.75 |
| Chitra Subramanian | 4 | 1 | 0.75 |
| horngchih lin | 5 | 1 | 0.75 |
| Syed M. Alam | 6 | 176 | 20.47 |
| Ken Papworth | 7 | 1 | 1.09 |
| W. L. Martino | 8 | 30 | 16.00 |