Name
Abstract | ||
|---|---|---|
In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates, which is 1.5 times higher than previously achieved efficiencies. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4542070 | Seattle, WA |
Keywords | Field | DocType |
CMOS integrated circuits,application specific integrated circuits,integrated circuit design,AES,ASIC,CAST-128,CLEFIA,CMOS standard cell library,Camellia,F-functions,ISO/IEC 18033-3 standard block ciphers,MISTY1,SEED,TDEA,hardware architectures,size 90 nm,word length 128 bit | Block cipher,MISTY1,Computer science,Electronic engineering,CLEFIA,CMOS,Application-specific integrated circuit,CAST-128,Standard cell,Embedded system,128-bit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 7 |
PageRank | References | Authors |
0.77 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takeshi Sugawara | 1 | 126 | 12.25 |
| Naofumi Homma | 2 | 377 | 53.81 |
| Takafumi Aoki | 3 | 915 | 125.99 |
| Akashi Satoh | 4 | 866 | 69.99 |