Name
Title | ||
|---|---|---|
A characterization of instruction-level error derating and its implications for error detection |
Abstract | ||
|---|---|---|
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which computation on incorrect values can result in cor- rect computation. We characterize the instruction-level derating that occurs in the SPEC CPU2000 INT bench- marks, classifying it (by source) into six categories: value comparison, sub-word operations, logical operations, over- flow/precision, lucky loads, and dynamically-dead values. We also characterize the temporal nature of this derating, demonstrating that the effects of a fault persist in archi- tectural state long after the last time they are referenced. Finally, we demonstrate how this characterization can be used to avoid unnecessary error recoveries (when a fault will be masked by software anyway) in the context of a dual modular redundant (DMR) architecture. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/DSN.2008.4630119 | Anchorage, AK |
Keywords | Field | DocType |
error detection,instruction sets,SPEC CPU2000 INT benchmarks,dual modular redundant architecture,error detection,instruction-level derating,instruction-level error,Dual modular redundancy,error detection,fault injection,instruction-level derating,software derating | Derating,Instruction set,Computer science,Real-time computing,Error detection and correction,Software,Dual modular redundancy,Modular design,Spec#,Fault injection | Conference |
ISSN | ISBN | Citations |
1530-0889 | 978-1-4244-2398-9 | 22 |
PageRank | References | Authors |
0.78 | 21 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeffrey J. Cook | 1 | 110 | 7.45 |
| Craig B. Zilles | 2 | 932 | 94.74 |