Name
Abstract | ||
|---|---|---|
Defects in the modern LSIs manufactured by the deep-submicron technologies are known to cause complex faulty phenomena. Testing by targeting only stuck-at or bridging faults is no longer sufficient. Yet, increasing defect coverage is even more important. A stuck-open fault model considers transistor level defects, many of which are not covered by a stuck-at fault model. Further, test vectors for stuck-open faults also have the ability to detect the defects modeled by delay faults. This paper presents test generation methods for stuck-open faults using stuck-at test vectors and stuck-at test generation tools. The resultant test vectors achieve high coverage of stuck open faults while maintaining the original stuck-at fault coverage, thus offering the benefit of potential better defect coverage. We consider two types of test application mechanisms, namely launch on capture test and enhanced scan test. The effectiveness of the proposed methods is established by experimental results for benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ATS.2008.39 | ATS |
Field | DocType | ISSN |
Stuck-at fault,Automatic test pattern generation,Fault coverage,Computer science,Bridging (networking),Combinational logic,Electronic engineering,Test compression,Computer engineering,Fault model,Reliability engineering,Benchmark (computing) | Conference | 1081-7735 |
Citations | PageRank | References |
7 | 0.64 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Kewal K. Saluja | 2 | 1483 | 141.49 |
| Hiroshi Takahashi | 3 | 148 | 24.32 |
| Shin-ya Kobayashi | 4 | 38 | 8.60 |
| Yuzo Takamatsu | 5 | 150 | 27.40 |