Paper Info
Title
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance
Abstract
A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.
Year
DOI
Venue
2012
10.1109/ICICDT.2012.6232860
ICICDT
Keywords
Field
DocType
cmos integrated circuits,sram chips,error correction codes,radiation hardening (electronics),cmos,bit-interleaved sram,bit-interleaving,energy 1.77 pj,energy 55 fj,energy gain,error correcting code,frequency 1 mhz,frequency 490 khz,low energy access,memory terrestrial radiation,radiation soft error tolerance,size 65 nm,soft error rate,transistor bitcell,ultra low voltage,voltage 0.32 v,voltage 0.4 v,voltage 1.2 v to 0.35 v,wafer level yield,error correction code,computer architecture,multiplexing,measurement,soft error,transistors,logic gate,logic gates
Logic gate,Soft error,Computer science,Voltage,Electronic engineering,Real-time computing,Error detection and correction,Static random-access memory,CMOS,Low voltage,Transistor,Electrical engineering
Conference
ISSN
ISBN
Citations 
pending E-ISBN : 978-1-4673-0144-2
978-1-4673-0144-2
1
PageRank 
References 
Authors
0.40
7
6
Name
Order
Citations
PageRank
Sylvain Clerc1368.56
Fady Abouzeid2326.98
Gilles Gasiot383.65
david gauthier410.40
Dimitri Soussan5212.81
Philippe Roche68516.31