Name
Abstract | ||
|---|---|---|
Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ReCoSoC.2012.6322881 | Reconfigurable Communication-centric Systems-on-Chip |
Keywords | Field | DocType |
customer satisfaction,field programmable gate arrays,logic design,microprocessor chips,performance evaluation,power aware computing,reconfigurable architectures,FASTER project,FASTER toolchain,FPGA,Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration project,complex reconfigurable systems,customer satisfaction,customer tracking,design time reduction,general purpose processor,hardware accelerators,hardware adaptation,high-level description,market trends,partial dynamic reconfiguration,performance efficiency,power efficiency,product lifetime,smart technologies,software adaptivity,system specification,technology trends,user applications,verification time reduction | Logic synthesis,Computer science,Field-programmable gate array,Real-time computing,Software,Electronics,System requirements specification,User requirements document,Toolchain,Control reconfiguration,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4673-2571-4 | 4 | 0.41 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marco D. Santambrogio | 1 | 771 | 91.15 |
| Dionisios N. Pnevmatikatos | 2 | 982 | 106.40 |
| catalin ciobanu | 3 | 19 | 1.88 |
| Christian Pilato | 4 | 329 | 32.19 |