Name
Title | ||
|---|---|---|
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains |
Abstract | ||
|---|---|---|
This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results are shown for two industrial designs. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TEST.2010.5699211 | Test Conference |
Keywords | Field | DocType |
automatic test pattern generation,clocks,logic testing,system-on-chip,ATPG technique,automated test,clock control architecture,clock control hardware,industrial designs,multiple clock domain SoC design,on-chip clock controllers,pattern count reducing,production test,system-on-chips | Automatic test pattern generation,Phase-locked loop,Synchronization,Logic gate,Architecture,System on a chip,Computer science,Clock control,Real-time computing,Electronic engineering,Digital clock manager,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-4244-7206-2 | 2 |
PageRank | References | Authors |
0.40 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tom Waayers | 1 | 128 | 11.47 |
| Richard Morren | 2 | 2 | 0.40 |
| Xijiang Lin | 3 | 687 | 42.03 |
| Mark Kassab | 4 | 654 | 48.74 |