Name
Abstract | ||
|---|---|---|
Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/DDECS.2011.5783071 | Design and Diagnostics of Electronic Circuits & Systems |
Keywords | Field | DocType |
SRAM chips,capacitance,fault diagnosis,logic testing,SRAM,defective node,faulty node voltage,memory testing,parasitic memory effect,parasitic node capacitance,single cell fault,Parasitic memory effect,SRAMs,static faults | Logic gate,Capacitance,Parasitic capacitance,Logic testing,Computer science,Voltage,Static random-access memory,Electronic engineering,Memory testing,Memory cell | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-4244-9755-3 | 1 |
PageRank | References | Authors |
0.37 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sandra Irobi | 1 | 8 | 2.05 |
| Zaid Al-Ars | 2 | 560 | 78.62 |
| Said Hamdioui | 3 | 887 | 118.69 |
| Michel Renovell | 4 | 749 | 96.46 |