Title
Practical evaluation of DPA countermeasures on reconfigurable hardware
Abstract
In CHES 2010 a correlation-based power analysis collision attack has been introduced which is supposed to exploit any first-order leakage of cryptographic devices. This work examines the effectiveness of the well-known DPA countermea-sures versus the correlation collision attack. The considered countermeasures include masking, shuffling, and noise addition, when applied in hardware. Practical evaluations, which all have been performed using power traces measured from an FPGA board, show an increase in the number of required traces, e.g. from 10,000 to 1,500,000, when combining different counter-measures. This study allows for a fair comparison between the hardware countermeasures and helps identifying an appropriate key lifetime.
Year
DOI
Venue
2011
10.1109/HST.2011.5955014
Hardware-Oriented Security and Trust
Keywords
Field
DocType
computer crime,cryptography,field programmable gate arrays,reconfigurable architectures,CHES 2010,DPA countermeasure,FPGA board,correlation based power analysis collision attack,cryptographic device,first order leakage,noise addition,reconfigurable hardware
Power analysis,Leakage (electronics),Computer science,Cryptography,Field-programmable gate array,Exploit,Real-time computing,Shuffling,Collision attack,Reconfigurable computing,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4577-1059-9
2
0.39
References 
Authors
12
3
Name
Order
Citations
PageRank
Amir Moradi196080.66
Oliver Mischke220411.53
Christof Paar33794442.62