| Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs | 6 | 0.46 | 2015 |
| Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives. | 0 | 0.34 | 2015 |
| Fault Sensitivity Analysis Meets Zero-Value Attack | 6 | 0.45 | 2014 |
| MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-. | 1 | 0.37 | 2014 |
| Comprehensive Evaluation of AES Dual Ciphers as a Side-Channel Countermeasure | 1 | 0.35 | 2013 |
| On the simplicity of converting leakages from multivariate to univariate: case study of a glitch-resistant masking scheme | 13 | 0.68 | 2013 |
| One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores | 10 | 0.57 | 2013 |
| Glitch-free implementation of masking in modern FPGAs. | 11 | 0.59 | 2012 |
| How far should theory be from practice?: evaluation of a countermeasure | 12 | 0.63 | 2012 |
| IPSecco: A lightweight and reconfigurable IPSec core | 4 | 0.45 | 2012 |
| Side channels as building blocks. | 5 | 0.46 | 2012 |
| Collision Timing Attack when Breaking 42 AES ASIC Cores. | 5 | 0.58 | 2011 |
| MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor | 12 | 0.61 | 2011 |
| On the power of fault sensitivity analysis and collision side-channel attacks in a combined setting | 28 | 1.25 | 2011 |
| Practical evaluation of DPA countermeasures on reconfigurable hardware | 2 | 0.39 | 2011 |
| Correlation-enhanced power analysis collision attack | 88 | 3.36 | 2010 |
