Name
Abstract | ||
|---|---|---|
This paper presents a study addressing the challenge of interfacing automatic test equipment (ATE) with on-chip decompression logic deployed by system-on-chip designs or modular decompression environments. The ability of the proposed scheme to improve the encoding bandwidth by reusing groups of scan chains for test data storage has been measured on industrial designs and is reported herein. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ETS.2011.13 | European Test Symposium |
Keywords | Field | DocType |
automatic test equipment,data compression,encoding,logic testing,system-on-chip,ATE interface,automatic test equipment,encoding bandwidth,high test data compression,industrial design,modular decompression environment,on-chip decompression logic,system-on-chip design,test data storage,channel bandwidth management,embedded deterministic test,scan-based designs,test data compression,test interface,tri-modal compression | Logic gate,System on a chip,Computer science,Automatic test equipment,Interfacing,Electronic engineering,Test data,Modular design,Computer hardware,Data compression,Encoding (memory),Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1877 E-ISBN : 978-0-7695-4433-5 | 978-0-7695-4433-5 | 2 |
PageRank | References | Authors |
0.39 | 27 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Czysz, D. | 1 | 2 | 0.39 |
| G. Mrugalski | 2 | 207 | 9.53 |
| Mukherjee, N. | 3 | 278 | 9.93 |
| J. Rajski | 4 | 985 | 63.36 |