Paper Info
Title
Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages
Abstract
BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, High-Speed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of Vdd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.
Year
DOI
Venue
2015
10.1109/IRPS.2015.7112783
Reliability Physics Symposium
Keywords
Field
DocType
mosfet circuits,spice,sram chips,circuit simulation,failure analysis,integrated circuit noise,negative bias temperature instability,6t sram cells,ac activity stress,bsim-cmg based hspice framework,dc activity stress,finfet based sram,nbti variability,critical failure situations,flip-time,high-density cells,high-speed cells,hold static noise margin,negative bias temperature instability variability,post-bti sram parameter variability,process corners,read static noise margin,stochastic bti impact,time-zero variability,bsim-cmg,finfet,hspice,nbti,reaction-diffusion model,snm,sram,variability,noise,stress,degradation
High-definition video,Static noise margin,Process corners,Spice,Voltage,Static random-access memory,Electronic engineering,Negative-bias temperature instability,Engineering
Conference
ISSN
Citations 
PageRank 
1541-7026
4
0.50
References 
Authors
7
4
Name
Order
Citations
PageRank
N. Goel1121.92
Dubey, P.240.50
Kawa, J.340.50
Mahapatra, S.4224.83