Name
Title | ||
|---|---|---|
Corrections to “Settling Time Optimization for Three-Stage CMOS Amplifier Topologies” [Dec 09 2569-2582] |
Abstract | ||
|---|---|---|
In the above titled paper (ibid., vol. 56, no. 12, pp. 2569-2582, Dec. 09), Tables IV and VI must be replaced. Due to a production error, the correct version of Table IV was not included, and Table VI contained an error in the PM value for NMC topology (6th row, 3rd column), The correct versions of Tables IV and VI are presented here. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2010.2055090 | IEEE Transactions on Circuits and Systems I-regular Papers |
Keywords | Field | DocType |
production,error correction,computer science,power dissipation,circuit topology | Cmos amplifier,Control theory,Settling time,Electronic engineering,Network topology,Error detection and correction,Computer errors,Mathematics,Topology (electrical circuits) | Journal |
Volume | Issue | ISSN |
57 | 7 | 1549-8328 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Pugliese | 1 | 3 | 1.56 |
| F. A. Amoroso | 2 | 6 | 3.70 |
| Gregorio Cappuccino | 3 | 36 | 10.11 |
| Giuseppe Cocorullo | 4 | 106 | 17.00 |